![]() Some of the advanced digital signal processing (DSP) applications demand more resources. Many researchers have worked on the design of multipliers earlier, as reported in this section, but they have not explored the option of reusing the same resources using iterative methods. The modern FPGAs have built-in multipliers in them but still the configurable multipliers using LUTs play a vital role in many applications due to their flexible size, placement and modification ability. George Walters III presents array multipliers using six-input LUTs and shift register LUTs , whereas the research presented in this article presents those using four-input LUTs. In , a multiplexer-based 8-bit multiplier is presented with 50 MHz frequency, whereas the proposed architecture achieves 320 MHz frequency for 16-bit multiplication. A two-dimensional bypassing technique is used in to design the multiplier, and the article focused on optimization of power consumption and delay, whereas the proposed approach presented in this article optimizes the resource consumption of FPGA. In , a re-configurable digit-serial multiplier is proposed which used clock gating for power optimization but this work does not optimize the resource consumption of FPGA. They exhibited different properties in balanced, area-optimized, timing performance and power-optimized modes. These tools have been realized in on Dadda, Booth, Array and Wallace multipliers. Xilinx also provides some tools to optimize the area, delay and power of the designed system. Wallace tree is also an advanced, pipelined, fast and highly used algorithm. ![]() An array multiplier is the simplest architecture but its drawback is its higher number of partial products as compared to the tree multipliers and hence it consumes more resources and time. The former is a high-speed algorithm as the partial products are generated and added concurrently while the latter one is more efficient in terms of hardware utilization. Researchers have also utilized Urdhva-Tiryakbhyam and Nikhilam multiplication algorithms. It solves numerous mathematical problems in 16 distinct ways. Vedic algorithm can be used to handle complex mathematical problems and logic design, and it is a fast and low-power algorithm. It was claimed that Radix-4 booth multiplier utilizes less resources and achieves high speed. Radix-2 and Radix-4 booth multipliers were implemented in for 8-bit and 16-bit multiplication. For multiplication of signed numbers, typically the Baugh-Wooley multiplier is preferred. The commonly used architectures include Baugh-Wooley and Booth multiplier. Multiplication is the most common, critical and widely used operation in many applications.
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